diff options
| author | Marian-Cristian Rotariu <[email protected]> | 2020-08-27 15:53:14 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2020-09-04 09:54:39 +0200 |
| commit | ff9e786f0ee0cc33aedabaa56678cb45d3c1ca0b (patch) | |
| tree | d040cb3433ec9869d6d0cdaf4b516a51a13b768e | |
| parent | a0be3c32b15675e9f9dc0d3dc4e0361c019b93d8 (diff) | |
arm64: dts: renesas: r8a774e1: Add FDP1 device nodes
Add FDP1 device nodes to R8A774E1 (RZ/G2H) SoC dtsi.
Signed-off-by: Marian-Cristian Rotariu <[email protected]>
Signed-off-by: Lad Prabhakar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index f5909ced7679..34fdb9a0c325 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2504,6 +2504,26 @@ renesas,fcp = <&fcpvi1>; }; + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 119>; + renesas,fcp = <&fcpf0>; + }; + + fdp1@fe944000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe944000 0 0x2400>; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 118>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 118>; + renesas,fcp = <&fcpf1>; + }; + fcpf0: fcp@fe950000 { compatible = "renesas,fcpf"; reg = <0 0xfe950000 0 0x200>; |