diff options
| author | Andrew Bresticker <[email protected]> | 2014-09-18 14:47:13 -0700 |
|---|---|---|
| committer | Ralf Baechle <[email protected]> | 2014-11-24 07:44:53 +0100 |
| commit | ff1e29ade4c677c24ee972549d20f07e466d50bf (patch) | |
| tree | 3e22a0a90b8b5163e24a4d21e4cc3eb957e6f772 | |
| parent | a669efc4a3b49de9226b280bb683f5b1d5a5d143 (diff) | |
MIPS: smp-cps: Enable all hardware interrupts on secondary CPUs
Currently interrupt vectors 2 and 5 are left disabled on secondary CPUs.
Since systems using CPS must also have a GIC, which is responsible for
routing all external interrupts and can map them to any hardware interrupt
vector, enable the remaining vectors. The two software interrupt vectors
are left disabled since they are not used with CPS.
Signed-off-by: Andrew Bresticker <[email protected]>
Reviewed-by: Qais Yousef <[email protected]>
Tested-by: Qais Yousef <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Andrew Bresticker <[email protected]>
Cc: Jeffrey Deans <[email protected]>
Cc: Markos Chandras <[email protected]>
Cc: Paul Burton <[email protected]>
Cc: Qais Yousef <[email protected]>
Cc: Jonas Gorski <[email protected]>
Cc: John Crispin <[email protected]>
Cc: David Daney <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/7803/
Signed-off-by: Ralf Baechle <[email protected]>
| -rw-r--r-- | arch/mips/kernel/smp-cps.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index e6e16a1d4add..cd20acad7f17 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -273,8 +273,8 @@ static void cps_init_secondary(void) if (cpu_has_mipsmt) dmt(); - change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | - STATUSF_IP6 | STATUSF_IP7); + change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 | + STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7); } static void cps_smp_finish(void) |