diff options
| author | Anshuman Khandual <[email protected]> | 2024-02-20 08:02:03 +0530 |
|---|---|---|
| committer | Catalin Marinas <[email protected]> | 2024-02-21 18:06:33 +0000 |
| commit | fdd867fe9b32c30b290aa10097f89daff09625cc (patch) | |
| tree | fc1627c7c6c9f293c754f6277536177c928b86cf | |
| parent | 54be6c6c5ae8e0d93a6c4641cb7528eb0b6ba478 (diff) | |
arm64/sysreg: Add register fields for ID_AA64DFR1_EL1
This adds register fields for ID_AA64DFR1_EL1 as per the definitions based
on DDI0601 2023-12.
Cc: Will Deacon <[email protected]>
Cc: Mark Brown <[email protected]>
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Anshuman Khandual <[email protected]>
Reviewed-by: Mark Brown <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Catalin Marinas <[email protected]>
| -rw-r--r-- | arch/arm64/tools/sysreg | 31 |
1 files changed, 30 insertions, 1 deletions
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 4c9b67934367..dd693f992832 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1251,7 +1251,36 @@ EndEnum EndSysreg Sysreg ID_AA64DFR1_EL1 3 0 0 5 1 -Res0 63:0 +Field 63:56 ABL_CMPs +UnsignedEnum 55:52 DPFZS + 0b0000 IGNR + 0b0001 FRZN +EndEnum +UnsignedEnum 51:48 EBEP + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 47:44 ITE + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 43:40 ABLE + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 39:36 PMICNTR + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 35:32 SPMU + 0b0000 NI + 0b0001 IMP + 0b0010 IMP_SPMZR +EndEnum +Field 31:24 CTX_CMPs +Field 23:16 WRPs +Field 15:8 BRPs +Field 7:0 SYSPMUID EndSysreg Sysreg ID_AA64AFR0_EL1 3 0 0 5 4 |