diff options
| author | Vijay Kumar <[email protected]> | 2017-07-28 19:29:32 -0600 |
|---|---|---|
| committer | David S. Miller <[email protected]> | 2017-08-04 11:08:53 -0700 |
| commit | fdaccf74fe83ab3438df014efd55788a1dd414b5 (patch) | |
| tree | 0757e25678012f450ddcfa31d24da36d534ed08d | |
| parent | 7d484acb2f90643de7e242fd47e48c3ebb22df3a (diff) | |
sparc64: Increase max_phys_bits to 51 and VA bits to 53 for M8.
On M8 chips, use a max_phys_bits value of 51.
Also, M8 supports VA bits up to 54 bits. However, for now
restrict VA bits to 53 due to 4-level pagetable limitation.
Signed-off-by: Vijay Kumar <[email protected]>
Reviewed-by: Bob Picco <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
| -rw-r--r-- | arch/sparc/mm/init_64.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c index c24f4bfc3b84..afa0099f3748 100644 --- a/arch/sparc/mm/init_64.c +++ b/arch/sparc/mm/init_64.c @@ -1944,12 +1944,22 @@ static void __init setup_page_offset(void) break; case SUN4V_CHIP_SPARC_M7: case SUN4V_CHIP_SPARC_SN: - default: /* M7 and later support 52-bit virtual addresses. */ sparc64_va_hole_top = 0xfff8000000000000UL; sparc64_va_hole_bottom = 0x0008000000000000UL; max_phys_bits = 49; break; + case SUN4V_CHIP_SPARC_M8: + default: + /* M8 and later support 54-bit virtual addresses. + * However, restricting M8 and above VA bits to 53 + * as 4-level page table cannot support more than + * 53 VA bits. + */ + sparc64_va_hole_top = 0xfff0000000000000UL; + sparc64_va_hole_bottom = 0x0010000000000000UL; + max_phys_bits = 51; + break; } } |