diff options
| author | Alex Bee <[email protected]> | 2023-11-19 13:13:40 +0100 |
|---|---|---|
| committer | Heiko Stuebner <[email protected]> | 2023-11-20 15:45:02 +0100 |
| commit | fd610e604837936440ef7c64ab6998b004631647 (patch) | |
| tree | 3378693e823d036740fd7ff0868050d434c85a1c | |
| parent | 4b12245e59efea81e19d1aa118f6f835b3e27b3a (diff) | |
ARM: dts: rockchip: Make usbphy the parent of SCLK_USB480M for RK3128
Without setting the parent for SCLK_USB480M the clock will use xin24m as
it's default parent.
While this is generally not an issue for the usb blocks to work, it becomes
an issue for RK3128 since SCLK_USB480M can be a parent for other HW blocks
(GPU, VPU, VIO), but they will never chose it, since it is currently always
running at OSC frequency which is to slow for their needs.
This sets the usb2 phy's output as SCLK_USB480M's parent and it's users
can chose it if desired.
Signed-off-by: Alex Bee <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
| -rw-r--r-- | arch/arm/boot/dts/rockchip/rk3128.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index b5dac1322631..4e8b38604ecd 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -266,6 +266,8 @@ clocks = <&cru SCLK_OTGPHY0>; clock-names = "phyclk"; clock-output-names = "usb480m_phy"; + assigned-clocks = <&cru SCLK_USB480M>; + assigned-clock-parents = <&usb2phy>; #clock-cells = <0>; status = "disabled"; |