diff options
| author | Eric Yang <[email protected]> | 2017-09-21 18:16:01 -0400 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2017-10-21 16:42:48 -0400 |
| commit | fcbbe3da0ab65dc114937857fce81902e3fa2a97 (patch) | |
| tree | bee5c33a07aebd551bce50ed98f4ce993e5f5c52 | |
| parent | d596e5d08da0a25be789432ed821e63db9ef72ac (diff) | |
drm/amd/display: Use active + border for bw validation
When doing SLS, KMD gives us clipped v_addressable with
border. This results in bw validation failure.
Signed-off-by: Eric Yang <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index cc99073b7a54..319450d9cfc1 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -364,7 +364,8 @@ static void pipe_ctx_to_e2e_pipe_params ( } - input->dest.vactive = pipe->stream->timing.v_addressable; + input->dest.vactive = pipe->stream->timing.v_addressable + pipe->stream->timing.v_border_top + + pipe->stream->timing.v_border_bottom; input->dest.recout_width = pipe->plane_res.scl_data.recout.width; input->dest.recout_height = pipe->plane_res.scl_data.recout.height; @@ -882,10 +883,11 @@ bool dcn_validate_bandwidth( v->htotal[input_idx] = pipe->stream->timing.h_total; v->vtotal[input_idx] = pipe->stream->timing.v_total; + v->vactive[input_idx] = pipe->stream->timing.v_addressable + + pipe->stream->timing.v_border_top + pipe->stream->timing.v_border_bottom; v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total - - pipe->stream->timing.v_addressable + - v->vactive[input_idx] - pipe->stream->timing.v_front_porch; - v->vactive[input_idx] = pipe->stream->timing.v_addressable; v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_khz / 1000.0f; if (!pipe->plane_state) { |