diff options
| author | Krzysztof Kozlowski <[email protected]> | 2023-01-19 11:54:34 +0100 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2023-02-08 17:23:38 -0800 |
| commit | fc0ff3e702013c8af39f9967daaef1e565f7d165 (patch) | |
| tree | ace511b0f67a02af4f65ded77692a361f68750f9 | |
| parent | 0daef104e4b1d945ac81cb10e35c29f82695b10a (diff) | |
arm64: dts: qcom: sm8350: fixup SDHCI interconnect arguments
After switching interconnects to 2 cells, the SDHCI interconnects need
to get one more argument.
Fixes: 4f287e31ff5f ("arm64: dts: qcom: sm8350: Use 2 interconnect cells")
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm8350.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 3e019f8b9039..0a422637b61f 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2547,8 +2547,8 @@ <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "core", "xo"; resets = <&gcc GCC_SDCC2_BCR>; - interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>; + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; iommus = <&apps_smmu 0x4a0 0x0>; power-domains = <&rpmhpd SM8350_CX>; |