diff options
| author | Philip Yang <[email protected]> | 2023-04-19 17:43:26 -0400 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2023-06-09 09:58:48 -0400 |
| commit | fc021438d0ab7863dc93f84a557af6dc6255b881 (patch) | |
| tree | 7060a19c1f1081d89891a446d10280bb766f27df | |
| parent | 610dab118ff5013d46069c828b58d576e0907b66 (diff) | |
drm/amdgpu: Enable NPS4 CPX mode
CPX compute mode is valid mode for NPS4 memory partition mode.
Signed-off-by: Philip Yang <[email protected]>
Reviewed-by: Lijo Lazar <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c index 848049db00ab..97011e7e031d 100644 --- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c +++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.c @@ -281,9 +281,9 @@ static bool __aqua_vanjaram_is_valid_mode(struct amdgpu_xcp_mgr *xcp_mgr, adev->gmc.num_mem_partitions == 4) && (num_xccs_per_xcp >= 2); case AMDGPU_CPX_PARTITION_MODE: - return (num_xcc > 1) && - (adev->gmc.num_mem_partitions == 1 || - adev->gmc.num_mem_partitions == num_xcc); + return ((num_xcc > 1) && + (adev->gmc.num_mem_partitions == 1 || adev->gmc.num_mem_partitions == 4) && + (num_xcc % adev->gmc.num_mem_partitions) == 0); default: return false; } |