diff options
| author | Matt Roper <[email protected]> | 2023-11-27 11:03:33 -0800 |
|---|---|---|
| committer | Rodrigo Vivi <[email protected]> | 2023-12-21 11:45:05 -0500 |
| commit | f91bacce8dbb5dcb395e1ab9750977fa70ad485e (patch) | |
| tree | e43ed50c98848bdb899ba8c2e7907b9dbc625aa8 | |
| parent | 812ec747a354e00f5e789f3cdcfbc80f98f1d71d (diff) | |
drm/xe/dg2: Drop Wa_22014600077
The workaround database has been updated to drop this workaround for all
DG2 variants.
Reviewed-by: Gustavo Sousa <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Matt Roper <[email protected]>
Signed-off-by: Rodrigo Vivi <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_gt_regs.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_wa.c | 21 |
2 files changed, 0 insertions, 22 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index cc27fe8fc363..686930aba77e 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -340,7 +340,6 @@ #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15) #define CACHE_MODE_SS XE_REG_MCR(0xe420, XE_REG_OPTION_MASKED) -#define ENABLE_EU_COUNT_FOR_TDL_FLUSH REG_BIT(10) #define DISABLE_ECC REG_BIT(5) #define ENABLE_PREFETCH_INTO_IC REG_BIT(3) diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index 81ae0232146e..e0853ab30c00 100644 --- a/drivers/gpu/drm/xe/xe_wa.c +++ b/drivers/gpu/drm/xe/xe_wa.c @@ -522,27 +522,6 @@ static const struct xe_rtp_entry_sr engine_was[] = { XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA)) }, - { XE_RTP_NAME("22014600077"), - XE_RTP_RULES(SUBPLATFORM(DG2, G11), GRAPHICS_STEP(B0, FOREVER), - ENGINE_CLASS(RENDER)), - XE_RTP_ACTIONS(SET(CACHE_MODE_SS, - ENABLE_EU_COUNT_FOR_TDL_FLUSH, - /* - * Wa_14012342262 write-only reg, so skip - * verification - */ - .read_mask = 0)) - }, - { XE_RTP_NAME("22014600077"), - XE_RTP_RULES(SUBPLATFORM(DG2, G10), ENGINE_CLASS(RENDER)), - XE_RTP_ACTIONS(SET(CACHE_MODE_SS, - ENABLE_EU_COUNT_FOR_TDL_FLUSH, - /* - * Wa_14012342262 write-only reg, so skip - * verification - */ - .read_mask = 0)) - }, { XE_RTP_NAME("14015150844"), XE_RTP_RULES(PLATFORM(DG2), FUNC(xe_rtp_match_first_render_or_compute)), XE_RTP_ACTIONS(SET(XEHP_HDC_CHICKEN0, DIS_ATOMIC_CHAINING_TYPED_WRITES, |