diff options
| author | Rafał Miłecki <[email protected]> | 2024-04-05 12:50:30 +0200 |
|---|---|---|
| committer | AngeloGioacchino Del Regno <[email protected]> | 2024-06-27 10:10:22 +0200 |
| commit | f80cfe9616b7448eca709a3e87ca57201cd5787c (patch) | |
| tree | 40285274b93797f5da0641b4889e5d35dbf3ff61 | |
| parent | f14cdf03d1b9c1ce45b3752a54c500c36d26d3dc (diff) | |
arm64: dts: mediatek: mt7981: fix code alignment for PWM clocks
Align "clocks" array entries to start at the same column.
Fixes: cf29427573cc ("arm64: dts: mediatek: Add initial MT7981B and Xiaomi AX3000T")
Signed-off-by: Rafał Miłecki <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 5674ac81d1f8..8a6263cc569c 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -86,10 +86,10 @@ compatible = "mediatek,mt7981-pwm"; reg = <0 0x10048000 0 0x1000>; clocks = <&infracfg CLK_INFRA_PWM_STA>, - <&infracfg CLK_INFRA_PWM_HCK>, - <&infracfg CLK_INFRA_PWM1_CK>, - <&infracfg CLK_INFRA_PWM2_CK>, - <&infracfg CLK_INFRA_PWM3_CK>; + <&infracfg CLK_INFRA_PWM_HCK>, + <&infracfg CLK_INFRA_PWM1_CK>, + <&infracfg CLK_INFRA_PWM2_CK>, + <&infracfg CLK_INFRA_PWM3_CK>; clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; #pwm-cells = <2>; }; |