diff options
| author | Rex-BC Chen <[email protected]> | 2022-05-16 19:11:29 +0800 |
|---|---|---|
| committer | Matthias Brugger <[email protected]> | 2022-06-07 18:26:33 +0200 |
| commit | f3ceebeb0c9bf2ceba87faa6bb77b6bee1f01d99 (patch) | |
| tree | 61b1215605ef9506cd057e2a5ee21af15d4dc623 | |
| parent | 95eacb24f3739df87690e0c96982b88a6b2dc2bf (diff) | |
arm64: dts: mediatek: Add MediaTek CCI node for MT8183
Add MediaTek CCI devfreq node for MT8183.
Signed-off-by: Andrew-sh.Cheng <[email protected]>
Signed-off-by: Rex-BC Chen <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Matthias Brugger <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 4 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 4 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8183.dtsi | 8 |
3 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index 8953dbf84f3e..7ac9864db9de 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -412,6 +412,10 @@ }; +&cci { + proc-supply = <&mt6358_vproc12_reg>; +}; + &cpu0 { proc-supply = <&mt6358_vproc12_reg>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 8d5bf73a9099..b035e06840e6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -230,6 +230,10 @@ status = "okay"; }; +&cci { + proc-supply = <&mt6358_vproc12_reg>; +}; + &cpu0 { proc-supply = <&mt6358_vproc12_reg>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index cecf96b628b7..21ec9f1ef406 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -280,6 +280,14 @@ }; }; + cci: cci { + compatible = "mediatek,mt8183-cci"; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cci", "intermediate"; + operating-points-v2 = <&cci_opp>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; |