diff options
| author | Le Ma <[email protected]> | 2021-12-04 18:59:08 +0800 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2021-12-14 17:49:50 -0500 |
| commit | f3a8076eb28cae1553958c629aecec479394bbe2 (patch) | |
| tree | d9f69a9fb90bb6352a95e056740c3716323a34db | |
| parent | 2585cf9dfaaddf00b069673f27bb3f8530e2039c (diff) | |
drm/amdgpu: correct register access for RLC_JUMP_TABLE_RESTORE
should count on GC IP base address
Signed-off-by: Le Ma <[email protected]>
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Cc: [email protected]
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index b305fd39874f..edb3e3b08eed 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -3070,8 +3070,8 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev) AMD_PG_SUPPORT_CP | AMD_PG_SUPPORT_GDS | AMD_PG_SUPPORT_RLC_SMU_HS)) { - WREG32(mmRLC_JUMP_TABLE_RESTORE, - adev->gfx.rlc.cp_table_gpu_addr >> 8); + WREG32_SOC15(GC, 0, mmRLC_JUMP_TABLE_RESTORE, + adev->gfx.rlc.cp_table_gpu_addr >> 8); gfx_v9_0_init_gfx_power_gating(adev); } } |