diff options
| author | Kristina Martsenko <[email protected]> | 2023-05-09 15:22:28 +0100 |
|---|---|---|
| committer | Catalin Marinas <[email protected]> | 2023-06-05 17:05:31 +0100 |
| commit | f32c053b9806e42209d40e9ce7ed6f7f8be3be3b (patch) | |
| tree | 60c8af8e37a4e91287a3b7207fec31235b9fff07 | |
| parent | 306b4c9f7120c485607cbbfa1ac3ecec005d8231 (diff) | |
arm64: mops: document boot requirements for MOPS
FEAT_MOPS introduces new instructions, we require that these
instructions not execute as UNDEFINED when we identify that the feature
is supported.
Signed-off-by: Kristina Martsenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Catalin Marinas <[email protected]>
| -rw-r--r-- | Documentation/arm64/booting.rst | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst index ffeccdd6bdac..b3bbf330ed0a 100644 --- a/Documentation/arm64/booting.rst +++ b/Documentation/arm64/booting.rst @@ -379,6 +379,12 @@ Before jumping into the kernel, the following conditions must be met: - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1. + For CPUs with Memory Copy and Memory Set instructions (FEAT_MOPS): + + - If the kernel is entered at EL1 and EL2 is present: + + - HCRX_EL2.MSCEn (bit 11) must be initialised to 0b1. + The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must enter the kernel in the same exception level. Where the values documented |