diff options
| author | Sagar Arun Kamble <[email protected]> | 2015-09-12 10:17:51 +0530 |
|---|---|---|
| committer | Daniel Vetter <[email protected]> | 2015-09-23 10:48:49 +0200 |
| commit | f2d2fe95072acd5404f8051b8bf1195c61a47fb5 (patch) | |
| tree | ed67b30bad8284560b65a478fbab2bb9058bb838 | |
| parent | 7a58bad0e63295dfa803973efcebc80cb730c7bd (diff) | |
drm/i915: WaRsDisableCoarsePowerGating
WaRsDisableCoarsePowerGating: Coarse Power Gating (CPG) needs to be
disabled for platforms prior to BXT B0 and SKL GT3/GT4 till E0.
v2: Added GT3/GT4 Check.
Change-Id: Ia3c4c16e050c88d3e259f601054875c812d69c3a
Signed-off-by: Sagar Arun Kamble <[email protected]>
Reviewed-by: Alex Dai <[email protected]>
[danvet: Align continuation properly.]
Signed-off-by: Daniel Vetter <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f52431b1a058..09be8fc590d5 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4877,11 +4877,14 @@ static void gen9_enable_rc6(struct drm_device *dev) /* * 3b: Enable Coarse Power Gating only when RC6 is enabled. - * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6. + * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. */ - I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? - GEN9_MEDIA_PG_ENABLE : 0); - + if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || + ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0))) + I915_WRITE(GEN9_PG_ENABLE, 0); + else + I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? + (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0); intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |