diff options
| author | Icenowy Zheng <[email protected]> | 2023-03-19 21:29:31 +0000 |
|---|---|---|
| committer | Jernej Skrabec <[email protected]> | 2023-03-23 21:57:33 +0100 |
| commit | f23ba46e0799fc701bcd429d22767932401e9ae8 (patch) | |
| tree | 6838446ee9f9b79511138d76b95a0ac6eff349ab | |
| parent | fce449f5ba9735a80a83fe636e0d6507902084a0 (diff) | |
ARM: dts: suniv: add USB-related device nodes
The suniv SoC has a USB OTG controller and a USB PHY like other
Allwinner SoCs.
Add their device tree node.
Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
Acked-by: Jernej Skrabec <[email protected]>
Signed-off-by: Andre Przywara <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jernej Skrabec <[email protected]>
| -rw-r--r-- | arch/arm/boot/dts/suniv-f1c100s.dtsi | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 9455d27e516e..111f8bbc2a80 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -133,6 +133,32 @@ #size-cells = <0>; }; + usb_otg: usb@1c13000 { + compatible = "allwinner,suniv-f1c100s-musb"; + reg = <0x01c13000 0x0400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + interrupts = <26>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + allwinner,sram = <&otg_sram 1>; + status = "disabled"; + }; + + usbphy: phy@1c13400 { + compatible = "allwinner,suniv-f1c100s-usb-phy"; + reg = <0x01c13400 0x10>; + reg-names = "phy_ctrl"; + clocks = <&ccu CLK_USB_PHY0>; + clock-names = "usb0_phy"; + resets = <&ccu RST_USB_PHY0>; + reset-names = "usb0_reset"; + #phy-cells = <1>; + status = "disabled"; + }; + ccu: clock@1c20000 { compatible = "allwinner,suniv-f1c100s-ccu"; reg = <0x01c20000 0x400>; |