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authorManivannan Sadhasivam <[email protected]>2024-03-21 16:46:38 +0530
committerBjorn Andersson <[email protected]>2024-04-21 12:28:49 -0500
commited9b196418d4e2fa4f6c27b61a92c2038e1ba04d (patch)
tree0a6b0879afbd48d988976c1c801ce705d853438b
parent0c4d19b125401957123989a25094972cf0e77670 (diff)
ARM: dts: qcom: ipq4019: Add PCIe bridge node
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
-rw-r--r--arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
index b198e2af5158..0fb65f2bbcdf 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
@@ -470,6 +470,16 @@
"phy_ahb";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
qpic_bam: dma-controller@7984000 {