diff options
| author | Manivannan Sadhasivam <[email protected]> | 2024-03-21 16:46:32 +0530 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2024-04-21 12:31:41 -0500 |
| commit | ed2f87cf51b4ffab1585553b798773c9131efa6e (patch) | |
| tree | 3dc763dcfa997db8db2f035e3db88abc49656dd4 | |
| parent | df307c906c48d1c8c6ffb9022907bfb6cb041da6 (diff) | |
arm64: dts: qcom: qcs404: Add PCIe bridge node
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/qcs404.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index a05d0234f7fc..ac451f378056 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -1516,6 +1516,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; }; |