diff options
| author | Connor Abbott <[email protected]> | 2024-04-30 11:43:20 +0100 |
|---|---|---|
| committer | Rob Clark <[email protected]> | 2024-06-21 13:41:43 -0700 |
| commit | ecbf9b3a82ec44c3010ce45352e719a8e5dd965f (patch) | |
| tree | b1f9b98aee7cabe431e7016031d91afa4526bad8 | |
| parent | 41fd54ef74b02233a419b4929d26662e5f105f46 (diff) | |
drm/msm/a7xx: Add missing register writes from downstream
This isn't known to fix anything yet, but it's a good idea to add it.
Signed-off-by: Connor Abbott <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Patchwork: https://patchwork.freedesktop.org/patch/592043/
Signed-off-by: Rob Clark <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 07c2cd2d5098..c98cdb1e9326 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1091,6 +1091,17 @@ static int hw_init(struct msm_gpu *gpu) BIT(6) | BIT(5) | BIT(3) | BIT(2) | BIT(1)); } + if (adreno_is_a750(adreno_gpu)) { + /* Disable ubwc merged UFC request feature */ + gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(19), BIT(19)); + + /* Enable TP flaghint and other performance settings */ + gpu_write(gpu, REG_A6XX_TPL1_DBG_ECO_CNTL1, 0xc0700); + } else if (adreno_is_a7xx(adreno_gpu)) { + /* Disable non-ubwc read reqs from passing write reqs */ + gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(11), BIT(11)); + } + /* Enable interrupts */ gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, adreno_is_a7xx(adreno_gpu) ? A7XX_INT_MASK : A6XX_INT_MASK); |