diff options
| author | Nicholas Kazlauskas <[email protected]> | 2022-09-08 14:17:01 -0400 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2022-09-27 17:56:29 -0400 |
| commit | ec669ef2e2cf277f3e73d842bb3bda1c3ea2ea73 (patch) | |
| tree | 471a59939447f571fe7f0597924426ad3db4a63a | |
| parent | dd37fba90e72a48998d9f0eb5497088ea2b02ad1 (diff) | |
drm/amd/display: Wrap OTG disable workaround with FIFO control
[Why]
The DIO FIFO will underflow if we turn off the OTG before we turn
off the FIFO.
Since this happens as part of the OTG workaround and we don't reset
the FIFO afterwards we see the error persist.
[How]
Add disable FIFO before the disable CRTC and enable FIFO after enabling
the CRTC.
Reviewed-by: Syed Hassan <[email protected]>
Acked-by: Jasdeep Dhillon <[email protected]>
Signed-off-by: Nicholas Kazlauskas <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c index 8559dcd80af0..4a15aa7a375f 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c @@ -130,11 +130,20 @@ static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state if (pipe->top_pipe || pipe->prev_odm_pipe) continue; if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) { + struct stream_encoder *stream_enc = pipe->stream_res.stream_enc; + if (disable) { + if (stream_enc && stream_enc->funcs->disable_fifo) + pipe->stream_res.stream_enc->funcs->disable_fifo(stream_enc); + pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg); reset_sync_context_for_pipe(dc, context, i); - } else + } else { pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); + + if (stream_enc && stream_enc->funcs->enable_fifo) + pipe->stream_res.stream_enc->funcs->enable_fifo(stream_enc); + } } } } |