diff options
| author | Rodrigo Siqueira <[email protected]> | 2024-07-22 20:33:40 -0600 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2024-08-07 18:14:47 -0400 |
| commit | eb880ffddd5da8a014669deaf7bb3e7e9ecd06f4 (patch) | |
| tree | 1cfb4a5615ac4e6be0c9643169f5567339fb3ef0 | |
| parent | 437cf8bb0e1a56fa0491610706ddafd04b3b1a9b (diff) | |
drm/amd/display: Add missing mcache registers
Add missing register programming for mcache in DCN401.
Reviewed-by: Aurabindo Pillai <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Rodrigo Siqueira <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
(cherry picked from commit a00a177055cced5cd2bb057a1ace9a95a286bc49)
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h index 26efeada4f41..bb46f30d11d0 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h @@ -138,7 +138,9 @@ void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context); SRI_ARR(DCHUBP_MALL_CONFIG, HUBP, id), \ SRI_ARR(DCHUBP_VMPG_CONFIG, HUBP, id), \ SRI_ARR(UCLK_PSTATE_FORCE, HUBPREQ, id), \ - HUBP_3DLUT_FL_REG_LIST_DCN401(id) + HUBP_3DLUT_FL_REG_LIST_DCN401(id), \ + SRI_ARR(DCSURF_VIEWPORT_MCACHE_SPLIT_COORDINATE, HUBP, id), \ + SRI_ARR(DCHUBP_MCACHEID_CONFIG, HUBP, id) /* ABM */ #define ABM_DCN401_REG_LIST_RI(id) \ |