diff options
| author | Jisheng Zhang <[email protected]> | 2017-07-18 14:48:21 +0800 |
|---|---|---|
| committer | Bjorn Helgaas <[email protected]> | 2017-08-02 16:51:24 -0500 |
| commit | e9be4d78618af2e0d5592d9556cf0bba210cfd1a (patch) | |
| tree | 954aba3da421f58a2648bd372af08eb95570b7da | |
| parent | 684a3a91da401195dbe33b7cef9472bca41c61b9 (diff) | |
PCI: dwc: designware: Test PCIE_ATU_ENABLE bit specifically
The ATU CTRL2 register is 32 bits, and bits other than the enable bit may
be set. To check whether the ATU is enabled or not, we should test the
enable bit specifically.
Signed-off-by: Jisheng Zhang <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Joao Pinto <[email protected]>
Acked-by: Jingoo Han <[email protected]>
| -rw-r--r-- | drivers/pci/dwc/pcie-designware.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c index ebcdce219acb..50cef47fc25d 100644 --- a/drivers/pci/dwc/pcie-designware.c +++ b/drivers/pci/dwc/pcie-designware.c @@ -178,7 +178,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, */ for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2); - if (val == PCIE_ATU_ENABLE) + if (val & PCIE_ATU_ENABLE) return; usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); |