diff options
| author | David Daney <[email protected]> | 2017-06-09 12:49:47 +0100 |
|---|---|---|
| committer | Marc Zyngier <[email protected]> | 2017-06-15 09:45:04 +0100 |
| commit | e982276d8f5c974b838fb22ba8d592feb039a544 (patch) | |
| tree | 05e8245384984e1e7e5f36f4b99d530ae93c92ac | |
| parent | e23f62f76acea232d4def5d4eb21709a2b575f14 (diff) | |
arm64: Add MIDR values for Cavium cn83XX SoCs
Tested-by: Alexander Graf <[email protected]>
Acked-by: David Daney <[email protected]>
Acked-by: Catalin Marinas <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Signed-off-by: David Daney <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Signed-off-by: Christoffer Dall <[email protected]>
| -rw-r--r-- | arch/arm64/include/asm/cputype.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 0984d1b3a8f2..235e77d98261 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -86,6 +86,7 @@ #define CAVIUM_CPU_PART_THUNDERX 0x0A1 #define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2 +#define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3 #define BRCM_CPU_PART_VULCAN 0x516 @@ -96,6 +97,7 @@ #define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) +#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1) #ifndef __ASSEMBLY__ |