diff options
| author | Dmitry Baryshkov <[email protected]> | 2021-02-10 16:34:58 +0300 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2021-03-18 09:35:42 -0500 |
| commit | e9269650db2f5b4aeeafced1a42b2e51d10bcdf5 (patch) | |
| tree | b971f81848383d89a5037cef04c33f63a7d1722e | |
| parent | eb97ccbba0fe5978cd73b133ee99203aab6ff2bf (diff) | |
arm64: dts: qcom: qrb5165-rb5: switch into using GPIO for SPI0 CS
On the GENI SPI controller is is not very efficient if the chip select
line is controlled by the QUP itself (see 37dd4b777942 ("arm64: dts:
qcom: sc7180: Provide pinconf for SPI to use GPIO for CS") for the
details). Configure SPI0 CS pin as a GPIO.
Signed-off-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Douglas Anderson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 973a61576f67..5f41de20aa22 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -949,7 +949,8 @@ &spi0 { status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs_gpio>; + cs-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>; can@0 { compatible = "microchip,mcp2518fd"; @@ -1352,7 +1353,7 @@ }; /* PINCTRL - additions to nodes defined in sm8250.dtsi */ -&qup_spi0_cs { +&qup_spi0_cs_gpio { drive-strength = <6>; bias-disable; }; |