diff options
| author | Kieran Bingham <[email protected]> | 2021-03-22 17:29:18 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2021-03-29 10:51:04 +0200 |
| commit | e91bb1464df74fc068bd8d26c5177bdedcf7c2d5 (patch) | |
| tree | f09ccf557fdcf73dd8016dc93398edd43bab0630 | |
| parent | 9d68a386644402be31c9d002655492b5a17c8979 (diff) | |
arm64: dts: renesas: r8a779a0: Add FCPVD support
Provide FCPVD support for the R-Car V3U SoC.
Signed-off-by: Kieran Bingham <[email protected]>
Reviewed-by: Laurent Pinchart <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 6f3eba4653a3..73036a5b8312 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -1102,6 +1102,22 @@ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; }; + fcpvd0: fcp@fea10000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea10000 0 0x200>; + clocks = <&cpg CPG_MOD 508>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 508>; + }; + + fcpvd1: fcp@fea11000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea11000 0 0x200>; + clocks = <&cpg CPG_MOD 509>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 509>; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; |