diff options
| author | Wolfram Sang <[email protected]> | 2021-09-15 15:48:27 +0200 |
|---|---|---|
| committer | Wolfram Sang <[email protected]> | 2021-09-29 23:02:59 +0200 |
| commit | e7f4264821a4ee07775f3775f8530cfa9a6d4b5d (patch) | |
| tree | 172c5ab7fbfd023ea7d99f48b9fa75bdd14d8cee | |
| parent | c073b25dad0c2668b73ae9e8652bc3b8012e762b (diff) | |
i2c: rcar: enable interrupts before starting transfer
We want to enable the interrupts _before_ starting the transfer because
it is good programming style and also the proposed order in the R-Car
manual. There is no difference in practice because it doesn't matter in
which order both conditions appear if we wait for both to happen.
Signed-off-by: Ryo Kataoka <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
Reviewed-by: Niklas Söderlund <[email protected]>
Reviewed-by: Ulrich Hecht <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
| -rw-r--r-- | drivers/i2c/busses/i2c-rcar.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c index bff9913c37b8..fc13511f4562 100644 --- a/drivers/i2c/busses/i2c-rcar.c +++ b/drivers/i2c/busses/i2c-rcar.c @@ -339,6 +339,9 @@ static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) priv->flags |= ID_LAST_MSG; rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg)); + if (!priv->atomic_xfer) + rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); + /* * We don't have a test case but the HW engineers say that the write order * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since @@ -354,9 +357,6 @@ static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); rcar_i2c_write(priv, ICMSR, 0); } - - if (!priv->atomic_xfer) - rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND); } static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv) |