diff options
author | Rajendra Nayak <[email protected]> | 2020-01-07 16:15:25 +0530 |
---|---|---|
committer | Bjorn Andersson <[email protected]> | 2020-02-25 20:52:55 -0800 |
commit | e7bb680f917d019c6be660b77139ea5d75ccb8b0 (patch) | |
tree | fd2bc10315723be1cdd61b7ca1a431daa25d36bb | |
parent | 71f873169a80729f1b5efeae88e84b5beafa73cb (diff) |
arm64: dts: qcom: sc7180: Add CPU capacity values
Specify the relative CPU capacity of all SC7180 cpu cores.
Signed-off-by: Rajendra Nayak <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
-rw-r--r-- | arch/arm64/boot/dts/qcom/sc7180.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 8ebfa2e2741d..c754b4bf3273 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -89,6 +89,7 @@ compatible = "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_0>; #cooling-cells = <2>; @@ -107,6 +108,7 @@ compatible = "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_100>; #cooling-cells = <2>; @@ -122,6 +124,7 @@ compatible = "arm,armv8"; reg = <0x0 0x200>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_200>; #cooling-cells = <2>; @@ -137,6 +140,7 @@ compatible = "arm,armv8"; reg = <0x0 0x300>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_300>; #cooling-cells = <2>; @@ -152,6 +156,7 @@ compatible = "arm,armv8"; reg = <0x0 0x400>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_400>; #cooling-cells = <2>; @@ -167,6 +172,7 @@ compatible = "arm,armv8"; reg = <0x0 0x500>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_500>; #cooling-cells = <2>; @@ -182,6 +188,7 @@ compatible = "arm,armv8"; reg = <0x0 0x600>; enable-method = "psci"; + capacity-dmips-mhz = <1740>; dynamic-power-coefficient = <405>; next-level-cache = <&L2_600>; #cooling-cells = <2>; @@ -197,6 +204,7 @@ compatible = "arm,armv8"; reg = <0x0 0x700>; enable-method = "psci"; + capacity-dmips-mhz = <1740>; dynamic-power-coefficient = <405>; next-level-cache = <&L2_700>; #cooling-cells = <2>; |