diff options
author | Rafał Miłecki <[email protected]> | 2024-02-14 07:12:32 +0100 |
---|---|---|
committer | Stephen Boyd <[email protected]> | 2024-02-21 20:56:37 -0800 |
commit | e77c6359a448e5609bd1e1587ecbb5e373028428 (patch) | |
tree | e917d6cfea16a23d3fa7b0101af5d2124f82acc2 | |
parent | 1e365996b24b6343877dc920f3c90e457f61cd57 (diff) |
dt-bindings: clock: mediatek: convert PCIESYS to the json-schema clock
This helps validating DTS files. Introduced changes:
1. Documented "reg" property
2. Dropped "syscon" as it was incorrectly used
3. Adjusted nodename, "compatible" and "reg" in example
Signed-off-by: Rafał Miłecki <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
-rw-r--r-- | Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt | 25 | ||||
-rw-r--r-- | Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesys.yaml | 45 |
2 files changed, 45 insertions, 25 deletions
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt deleted file mode 100644 index d179a61536f4..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt +++ /dev/null @@ -1,25 +0,0 @@ -MediaTek PCIESYS controller -============================ - -The MediaTek PCIESYS controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be: - - "mediatek,mt7622-pciesys", "syscon" - - "mediatek,mt7629-pciesys", "syscon" -- #clock-cells: Must be 1 -- #reset-cells: Must be 1 - -The PCIESYS controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Example: - -pciesys: pciesys@1a100800 { - compatible = "mediatek,mt7622-pciesys", "syscon"; - reg = <0 0x1a100800 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesys.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesys.yaml new file mode 100644 index 000000000000..c77111d10f90 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesys.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt7622-pciesys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek PCIESYS clock and reset controller + +description: + The MediaTek PCIESYS controller provides various clocks to the system. + +maintainers: + - Matthias Brugger <[email protected]> + +properties: + compatible: + enum: + - mediatek,mt7622-pciesys + - mediatek,mt7629-pciesys + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + description: The available clocks are defined in dt-bindings/clock/mt*-clk.h + + "#reset-cells": + const: 1 + +required: + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@1a100800 { + compatible = "mediatek,mt7622-pciesys"; + reg = <0x1a100800 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; |