diff options
| author | Ian Rogers <irogers@google.com> | 2023-03-24 00:22:16 -0700 |
|---|---|---|
| committer | Arnaldo Carvalho de Melo <acme@redhat.com> | 2023-04-04 09:39:55 -0300 |
| commit | e559b6f53b1b36fd69291962104fa86edf3dadf4 (patch) | |
| tree | ae77f8d40e32b48252343da30ec98767c2477544 | |
| parent | 101a25b5d96d5ca06e11d07bb83fd72886407fe4 (diff) | |
perf vendor events intel: Sandybridge v19 events
Adds BR_MISP_EXEC.INDIRECT event.
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Samantha Alt <samantha.alt@intel.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20230324072218.181880-2-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/mapfile.csv | 2 | ||||
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json | 8 |
2 files changed, 9 insertions, 1 deletions
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index e41c289fa427..41d755d570e6 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -21,7 +21,7 @@ GenuineIntel-6-(57|85),v10,knightslanding,core GenuineIntel-6-A[AC],v1.01,meteorlake,core GenuineIntel-6-1[AEF],v3,nehalemep,core GenuineIntel-6-2E,v3,nehalemex,core -GenuineIntel-6-2A,v18,sandybridge,core +GenuineIntel-6-2A,v19,sandybridge,core GenuineIntel-6-(8F|CF),v1.11,sapphirerapids,core GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v55,skylake,core diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json b/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json index 54454e5e262c..ecaf94ccc9c7 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json @@ -211,6 +211,14 @@ "UMask": "0xc4" }, { + "BriefDescription": "Speculative mispredicted indirect branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.INDIRECT", + "PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, + { "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", |