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authorPhil Elwell <[email protected]>2017-05-15 10:35:04 -0700
committerStephen Boyd <[email protected]>2017-06-02 15:41:49 -0700
commite45098d703fbb9a7b02eae581aadb684b31e0eec (patch)
treeb132afa1028409d0435f8f350c563f0b534abb9e
parent887541159c5e4a89779c021553f89df9596ddd94 (diff)
clk: bcm2835: Correct the prediv logic
If a clock has the prediv flag set, both the integer and fractional parts must be scaled when calculating the resulting frequency. Signed-off-by: Phil Elwell <[email protected]> Signed-off-by: Eric Anholt <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
-rw-r--r--drivers/clk/bcm/clk-bcm2835.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 025853870619..7a35df6b45bd 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -616,8 +616,10 @@ static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw,
using_prediv = cprman_read(cprman, data->ana_reg_base + 4) &
data->ana->fb_prediv_mask;
- if (using_prediv)
+ if (using_prediv) {
ndiv *= 2;
+ fdiv *= 2;
+ }
return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv);
}