diff options
| author | Kishon Vijay Abraham I <[email protected]> | 2020-09-30 15:20:31 +0300 |
|---|---|---|
| committer | Nishanth Menon <[email protected]> | 2020-09-30 07:34:03 -0500 |
| commit | e38a45b0192c4562e610c9c81e4c742b48fa69f0 (patch) | |
| tree | 7dd30e2b7ee79f3c0cd306a1e71530582337df62 | |
| parent | 6197d7139d128d3391a94bfad467ffe349a869a6 (diff) | |
arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function
First two lanes of SERDES is connected to PCIe, third lane is
connected to QSGMII and the last lane is connected to USB. However,
Cadence torrent SERDES doesn't support more than 2 protocols
at the same time. Configure it only for PCIe and QSGMII.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Reviewed-by: Vignesh Raghavendra <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 1541311cecb4..ddbc2163e698 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -7,6 +7,7 @@ #include "k3-j7200-som-p0.dtsi" #include <dt-bindings/net/ti-dp83867.h> +#include <dt-bindings/mux/ti-serdes.h> / { chosen { @@ -185,3 +186,8 @@ ti,driver-strength-ohm = <50>; disable-wp; }; + +&serdes_ln_ctrl { + idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>, + <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>; +}; |