diff options
| author | Chanho Park <[email protected]> | 2021-10-18 21:42:04 +0900 |
|---|---|---|
| committer | Martin K. Petersen <[email protected]> | 2021-10-27 23:10:10 -0400 |
| commit | e387d448e4899f4bbf7c8151472a2fed72063d82 (patch) | |
| tree | 3661df1fb6c8d0a29de4b5aa82de8959977de782 | |
| parent | 10fb4f87438d99b2ef06aea38ca2f0454725e8b5 (diff) | |
scsi: ufs: ufs-exynos: Change pclk available max value
To support 167MHz PCLK, we need to adjust the maximum value.
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Alim Akhtar <[email protected]>
Reviewed-by: Inki Dae <[email protected]>
Signed-off-by: Chanho Park <[email protected]>
Signed-off-by: Martin K. Petersen <[email protected]>
| -rw-r--r-- | drivers/scsi/ufs/ufs-exynos.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h index dadf4fd10dd8..0a31f77a5f48 100644 --- a/drivers/scsi/ufs/ufs-exynos.h +++ b/drivers/scsi/ufs/ufs-exynos.h @@ -99,7 +99,7 @@ struct exynos_ufs; #define PA_HIBERN8TIME_VAL 0x20 #define PCLK_AVAIL_MIN 70000000 -#define PCLK_AVAIL_MAX 133000000 +#define PCLK_AVAIL_MAX 167000000 struct exynos_ufs_uic_attr { /* TX Attributes */ |