diff options
author | Lorenzo Bianconi <[email protected]> | 2024-06-15 23:15:41 +0200 |
---|---|---|
committer | Vinod Koul <[email protected]> | 2024-06-20 21:59:21 +0530 |
commit | e2d0317e665884d78c56f99d2a0005213d8390b6 (patch) | |
tree | cf9b09802f11e2ea2c59beb22f740556590c72a3 | |
parent | aefa036be8c216c8b344d34c9f35ff907b9c315a (diff) |
dt-bindings: phy: airoha: Add PCIe PHY controller
Introduce device-tree binding documentation for Airoha EN7581 PCIe PHY
controller.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: Lorenzo Bianconi <[email protected]>
Link: https://lore.kernel.org/r/656133f865433c1d02f00a3abbb1aa9312d2a24e.1718485860.git.lorenzo@kernel.org
Signed-off-by: Vinod Koul <[email protected]>
-rw-r--r-- | Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml new file mode 100644 index 000000000000..e26c30d17ff0 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/airoha,en7581-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha EN7581 PCI-Express PHY + +maintainers: + - Lorenzo Bianconi <[email protected]> + +description: + The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port. + +properties: + compatible: + const: airoha,en7581-pcie-phy + + reg: + items: + - description: PCIE analog base address + - description: PCIE lane0 base address + - description: PCIE lane1 base address + + reg-names: + items: + - const: csr-2l + - const: pma0 + - const: pma1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/phy/phy.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + phy@11e80000 { + compatible = "airoha,en7581-pcie-phy"; + #phy-cells = <0>; + reg = <0x0 0x1fa5a000 0x0 0xfff>, + <0x0 0x1fa5b000 0x0 0xfff>, + <0x0 0x1fa5c000 0x0 0xfff>; + reg-names = "csr-2l", "pma0", "pma1"; + }; + }; |