diff options
| author | Andre Przywara <[email protected]> | 2022-11-07 00:54:29 +0000 |
|---|---|---|
| committer | Jernej Skrabec <[email protected]> | 2022-11-16 19:38:07 +0100 |
| commit | e1d7dc52c3e629540401bf88cbdd8acaa5aea9de (patch) | |
| tree | ca5e7cddbcbdd1053bf1a5b818993856d7c1f867 | |
| parent | b9595d121143ef471ac1452d82491d300bf79238 (diff) | |
ARM: dts: suniv: f1c100s: add CIR DT node
The CIR (infrared receiver) controller in the Allwinner F1C100s series
of SoCs is compatible to the ones used in other Allwinner SoCs.
Add the DT node describing the resources of the controller.
There are multiple possible pinmuxes, but none as them seem to be an
obvious choice, so refrain from adding any pincontroller subnodes for
now.
Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jernej Skrabec <[email protected]>
| -rw-r--r-- | arch/arm/boot/dts/suniv-f1c100s.dtsi | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 115fbea1fef6..2db99fb352e6 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -243,6 +243,17 @@ status = "disabled"; }; + ir: ir@1c22c00 { + compatible = "allwinner,suniv-f1c100s-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x01c22c00 0x400>; + clocks = <&ccu CLK_BUS_IR>, <&ccu CLK_IR>; + clock-names = "apb", "ir"; + resets = <&ccu RST_BUS_IR>; + interrupts = <6>; + status = "disabled"; + }; + uart0: serial@1c25000 { compatible = "snps,dw-apb-uart"; reg = <0x01c25000 0x400>; |