diff options
| author | Konrad Dybcio <[email protected]> | 2023-07-31 14:20:13 +0200 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2023-08-17 20:09:11 -0700 |
| commit | e1cd74b6dccb98ca09e4612ff29c7658db7a487b (patch) | |
| tree | 3ed8e035bd7bf9ee6daff7cad04fe84e659fcda8 | |
| parent | 2db8dc7bf49cc0b04a99d9525d5d54312f431ce5 (diff) | |
clk: qcom: smd-rpm: Set XO rate and CLK_IS_CRITICAL on PCNoC
On all supported SoCs to date, the PCNoC (a.k.a CNoC_PERIPH) clock must
be always-on as long as the APSS is online and only has to run
at 19.2 MHz. Define it to be as such in the ACTIVE domain.
Some SoCs use that clock for bus scaling, while others just need it for
reaching the hardware. This commit will hurt neither.
Signed-off-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
| -rw-r--r-- | drivers/clk/qcom/clk-smd-rpm.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index f38eb8055759..c8d59e0f25f2 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -456,7 +456,7 @@ DEFINE_CLK_SMD_RPM_BRANCH(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2, 1000); DEFINE_CLK_SMD_RPM(aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1); DEFINE_CLK_SMD_RPM(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2); -DEFINE_CLK_SMD_RPM_BUS(pcnoc, 0); +DEFINE_CLK_SMD_RPM_BUS_A(pcnoc, 0, 19200000, CLK_IS_CRITICAL); DEFINE_CLK_SMD_RPM_BUS(snoc, 1); DEFINE_CLK_SMD_RPM_BUS(sysmmnoc, 2); DEFINE_CLK_SMD_RPM_BUS(cnoc, 2); |