diff options
| author | Aleksandar Markovic <[email protected]> | 2017-08-21 14:24:49 +0200 |
|---|---|---|
| committer | Ralf Baechle <[email protected]> | 2017-08-29 15:21:56 +0200 |
| commit | e1231dd6b1cfbed9dfda5de488ce23c2414e1f04 (patch) | |
| tree | aa09df505ad525f042e9fabd4e698afb8163b73d | |
| parent | 3ec404d88cefbe42d96a46f20f554f8366d64c33 (diff) | |
MIPS: math-emu: CLASS.D: Zero bits 32-63 of the result
Fix content of CLASS.D output bits 32-63 to match hardware behavior.
Prior to this patch, bits 32-63 of CLASS.D output were not
initialized, causing different 32-63 bits content of CLASS.D, based on
circumstances. However, the hardware consistently returns all these
bits zeroed. The documentation is not clear whether these bits should
be zero or unpredictable. Since technically "all zero" case still can
be viewed as belonging to "unpredictable" class of results, it is
better to zero bits 32-63.
Signed-off-by: Miodrag Dinic <[email protected]>
Signed-off-by: Goran Ferenc <[email protected]>
Signed-off-by: Aleksandar Markovic <[email protected]>
Cc: Douglas Leung <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Maciej W. Rozycki <[email protected]>
Cc: Masahiro Yamada <[email protected]>
Cc: Paul Burton <[email protected]>
Cc: Petar Jovanovic <[email protected]>
Cc: Raghu Gandham <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/17142/
Signed-off-by: Ralf Baechle <[email protected]>
| -rw-r--r-- | arch/mips/math-emu/cp1emu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 58396cb2057a..a4df2200c725 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -2144,8 +2144,8 @@ copcsr: return SIGILL; DPFROMREG(fs, MIPSInst_FS(ir)); - rv.w = ieee754dp_2008class(fs); - rfmt = w_fmt; + rv.l = ieee754dp_2008class(fs); + rfmt = l_fmt; break; } |