diff options
| author | Dave Jones <[email protected]> | 2009-11-10 15:01:20 -0500 |
|---|---|---|
| committer | Ingo Molnar <[email protected]> | 2009-11-10 21:52:32 +0100 |
| commit | e02e0e1a130b9ca37c5186d38ad4b3aaf58bb149 (patch) | |
| tree | 3d3d1b5c31be845ad760255a81c57c1a3acb47d0 | |
| parent | 85160b92fbd35321104819283c91bfed2b553e3c (diff) | |
x86: Fix typo in Intel CPU cache size descriptor
I double-checked the datasheet. One of the existing
descriptors has a typo: it should be 2MB not 2038 KB.
Signed-off-by: Dave Jones <[email protected]>
Cc: <[email protected]> # .3x.x: 85160b9: x86: Add new Intel CPU cache size descriptors
Cc: <[email protected]> # .3x.x
LKML-Reference: <[email protected]>
Signed-off-by: Ingo Molnar <[email protected]>
| -rw-r--r-- | arch/x86/kernel/cpu/intel_cacheinfo.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index 14103924b627..8178d0352935 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c @@ -94,7 +94,7 @@ static const struct _cache_table __cpuinitconst cache_table[] = { 0xd1, LVL_3, 1024 }, /* 4-way set assoc, 64 byte line size */ { 0xd2, LVL_3, 2048 }, /* 4-way set assoc, 64 byte line size */ { 0xd6, LVL_3, 1024 }, /* 8-way set assoc, 64 byte line size */ - { 0xd7, LVL_3, 2038 }, /* 8-way set assoc, 64 byte line size */ + { 0xd7, LVL_3, 2048 }, /* 8-way set assoc, 64 byte line size */ { 0xd8, LVL_3, 4096 }, /* 12-way set assoc, 64 byte line size */ { 0xdc, LVL_3, 2048 }, /* 12-way set assoc, 64 byte line size */ { 0xdd, LVL_3, 4096 }, /* 12-way set assoc, 64 byte line size */ |