diff options
| author | Stefan Agner <[email protected]> | 2015-05-27 14:47:52 +0200 |
|---|---|---|
| committer | Shawn Guo <[email protected]> | 2015-08-11 23:15:25 +0800 |
| commit | def0641e2f61a545a852887e15a19231c4c863c4 (patch) | |
| tree | a28a37c39339d45fa91cfc32e2f8c85931126a95 | |
| parent | abb9f253cd9873f1826c4accdad89ec3fe80de21 (diff) | |
ARM: dts: add property for maximum ADC clock frequencies
The ADC clock frequency is limited depending on modes used. Add
device tree property which allow to set the mode used and the
maximum frequency ratings for the instance. These allows to
set the ADC clock to a frequency which is within specification
according to the actual mode used.
Acked-by: Fugang Duan <[email protected]>
Signed-off-by: Stefan Agner <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
| -rw-r--r-- | arch/arm/boot/dts/vfxxx.dtsi | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi index c0f05ee77ae5..6865137fd114 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -228,6 +228,8 @@ clock-names = "adc"; #io-channel-cells = <1>; status = "disabled"; + fsl,adck-max-frequency = <30000000>, <40000000>, + <20000000>; }; wdoga5: wdog@4003e000 { @@ -470,6 +472,8 @@ <&clks VF610_CLK_ESDHC0>; clock-names = "ipg", "ahb", "per"; status = "disabled"; + fsl,adck-max-frequency = <30000000>, <40000000>, + <20000000>; }; esdhc1: esdhc@400b2000 { |