diff options
author | Serge Semin <[email protected]> | 2020-05-29 16:11:50 +0300 |
---|---|---|
committer | Mark Brown <[email protected]> | 2020-05-29 15:55:42 +0100 |
commit | de4c2875a5ff2c886df60f2086c6affca83f890a (patch) | |
tree | b579db09868ce0b958a2ab88e5a38a7958a6a2ff | |
parent | b7d73cb63cbac70746ee0d506aa2fa16b5dc75a0 (diff) |
spi: dw: Set xfer effective_speed_hz
Seeing DW APB SSI controller doesn't support setting the exactly
requested SPI bus frequency, but only a rounded frequency determined
by means of the odd-numbered half-worded reference clock divider,
it would be good to tune the SPI core up and initialize the current
transfer effective_speed_hz. By doing so the core will be able to
execute the xfer-related delays with better accuracy.
Signed-off-by: Serge Semin <[email protected]>
Cc: Georgy Vlasov <[email protected]>
Cc: Ramil Zaripov <[email protected]>
Cc: Alexey Malahov <[email protected]>
Cc: Thomas Bogendoerfer <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Feng Tang <[email protected]>
Cc: Andy Shevchenko <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: [email protected]
Cc: [email protected]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
-rw-r--r-- | drivers/spi/spi-dw.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index 1edb8cdd11ee..e6fc0bcf214d 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -352,6 +352,7 @@ static int dw_spi_transfer_one(struct spi_controller *master, spi_set_clk(dws, chip->clk_div); } + transfer->effective_speed_hz = dws->max_freq / chip->clk_div; dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE); cr0 = dws->update_cr0(master, spi, transfer); |