diff options
| author | Biju Das <[email protected]> | 2023-09-18 13:33:54 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2023-09-26 09:44:51 +0200 |
| commit | dd462cf53e4dff0f4eba5e6650e31ceddec74c6f (patch) | |
| tree | d8a34275f7b5c610c8bbcbec759b86e3bc60498e | |
| parent | 84c580e9695084d688904a18bfdc129aeca78144 (diff) | |
pinctrl: renesas: rzg2l: Make reverse order of enable() for disable()
We usually do reverse order of enable() for disable(). Currently, the
ordering of irq_chip_disable_parent() is not correct in
rzg2l_gpio_irq_disable(). Fix the incorrect order.
Fixes: db2e5f21a48e ("pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt")
Signed-off-by: Biju Das <[email protected]>
Tested-by: Claudiu Beznea <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
| -rw-r--r-- | drivers/pinctrl/renesas/pinctrl-rzg2l.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index b884f53557db..23c2a1044089 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1175,6 +1175,8 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d) u32 port; u8 bit; + irq_chip_disable_parent(d); + port = RZG2L_PIN_ID_TO_PORT(hwirq); bit = RZG2L_PIN_ID_TO_PIN(hwirq); @@ -1189,7 +1191,6 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d) spin_unlock_irqrestore(&pctrl->lock, flags); gpiochip_disable_irq(gc, hwirq); - irq_chip_disable_parent(d); } static void rzg2l_gpio_irq_enable(struct irq_data *d) |