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authorChun-Jie Chen <[email protected]>2022-10-14 18:20:29 +0800
committerMatthias Brugger <[email protected]>2022-12-16 11:41:18 +0100
commitdba8eb83af9dd757ef645b52200775e86883d858 (patch)
treefaef8f629abe0d19ff372b5026bf87be70dcd936
parent830b3c68c1fb1e9176028d02ef86f3cf76aa2476 (diff)
soc: mediatek: pm-domains: Fix the power glitch issue
Power reset maybe generate unexpected signal. In order to avoid the glitch issue, we need to enable isolation first to guarantee the stable signal when power reset is triggered. Fixes: 59b644b01cf4 ("soc: mediatek: Add MediaTek SCPSYS power domains") Signed-off-by: Chun-Jie Chen <[email protected]> Signed-off-by: Allen-KH Cheng <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Reviewed-by: Miles Chen <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
-rw-r--r--drivers/soc/mediatek/mtk-pm-domains.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index 09e3c38b8466..474b272f9b02 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -275,9 +275,9 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks);
/* subsys power off */
- regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT);
regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT);
+ regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT);
regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT);