diff options
| author | Alibek Omarov <[email protected]> | 2023-06-14 16:47:50 +0300 |
|---|---|---|
| committer | Heiko Stuebner <[email protected]> | 2023-07-10 12:11:26 +0200 |
| commit | dafebd0f9a4f56b10d7fbda0bff1f540d16a2ea4 (patch) | |
| tree | 80b4c0498d2d95352b0efc34e7b4096ff48ecc73 | |
| parent | 7f890a885f9a226ae1309b967d4e6fac933610db (diff) | |
clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
PLL rate on RK356x is calculated through the simple formula:
((24000000 / _refdiv) * _fbdiv) / (_postdiv1 * _postdiv2)
The PLL rate setting for 78.75MHz seems to be copied from 96MHz
so this patch fixes it and configures it properly.
Signed-off-by: Alibek Omarov <[email protected]>
Fixes: 842f4cb72639 ("clk: rockchip: Add more PLL rates for rk3568")
Reviewed-by: Sascha Hauer <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3568.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 5dae960af4ce..48b8d06c305c 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -82,7 +82,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0), RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0), RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0), - RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0), + RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0), RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0), { /* sentinel */ }, }; |