diff options
| author | Pali Rohár <[email protected]> | 2022-01-04 16:35:27 +0100 |
|---|---|---|
| committer | Lorenzo Pieralisi <[email protected]> | 2022-02-03 10:54:06 +0000 |
| commit | d76a6ed0964af14327068408da095a2355a5b8dc (patch) | |
| tree | e670356d8769fe358b45da6b597cca847d993ce5 | |
| parent | 16038ebb0f9f7daa685a439b4ee973c9dbd1416f (diff) | |
PCI: mvebu: Update comment for PCI_EXP_LNKCAP register on emulated bridge
Reason for clearing this bit is because mvebu hw returns incorrectly this bit set to 1.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Pali Rohár <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
| -rw-r--r-- | drivers/pci/controller/pci-mvebu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index 1a03fb353084..216da126a06d 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -546,8 +546,8 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, case PCI_EXP_LNKCAP: /* - * PCIe requires the clock power management capability to be - * hard-wired to zero for downstream ports + * PCIe requires that the Clock Power Management capability bit + * is hard-wired to zero for downstream ports but HW returns 1. */ *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) & ~PCI_EXP_LNKCAP_CLKPM; |