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| author | Alexandre Ghiti <[email protected]> | 2024-07-17 08:01:23 +0200 |
|---|---|---|
| committer | Palmer Dabbelt <[email protected]> | 2024-09-15 00:11:03 -0700 |
| commit | d25599b5933fb5f89d4b4c720564d613a795f502 (patch) | |
| tree | 302acc941664952e0bf46f80b0929115587f2766 | |
| parent | a6efe33cc5945c8d435d2441ecc4e0ca7c49e040 (diff) | |
dt-bindings: riscv: Add Svvptc ISA extension description
Add description for the Svvptc ISA extension which was ratified recently.
Signed-off-by: Alexandre Ghiti <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/extensions.yaml | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 468c646247aa..b52375bea512 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -171,6 +171,13 @@ properties: memory types as ratified in the 20191213 version of the privileged ISA specification. + - const: svvptc + description: + The standard Svvptc supervisor-level extension for + address-translation cache behaviour with respect to invalid entries + as ratified at commit 4a69197e5617 ("Update to ratified state") of + riscv-svvptc. + - const: zacas description: | The Zacas extension for Atomic Compare-and-Swap (CAS) instructions |