diff options
| author | Heiko Stuebner <[email protected]> | 2022-07-07 01:15:34 +0200 |
|---|---|---|
| committer | Palmer Dabbelt <[email protected]> | 2022-07-28 15:30:21 -0700 |
| commit | d1afce6709595b39cd159bdc54fe2093808c02fc (patch) | |
| tree | cb843252c84cbccb9b525b67e5c5910bc8dcb262 | |
| parent | 12b827758f51d4b614a677dd453b0e854e46aa65 (diff) | |
dt-bindings: riscv: document cbom-block-size
The Zicbom operates on a block-size defined for the cpu-core,
which does not necessarily match other cache-sizes used.
So add the necessary property for the system to know the core's
block-size.
Reviewed-by: Anup Patel <[email protected]>
Reviewed-by: Guo Ren <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d632ac76532e..873dd12f6e89 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -63,6 +63,11 @@ properties: - riscv,sv48 - riscv,none + riscv,cbom-block-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The blocksize in bytes for the Zicbom cache operations. + riscv,isa: description: Identifies the specific RISC-V instruction set architecture |