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authorTushar Dave <[email protected]>2012-07-12 08:56:56 +0000
committerJeff Kirsher <[email protected]>2012-07-14 00:43:27 -0700
commitd0efa8f23a644f7cb7d1f8e78dd9a223efa412a3 (patch)
tree6211ea45128d665f9489cada230fec0ef62da221
parent7ac2908e4b2edaec60e9090ddb4d9ceb76c05e7d (diff)
e1000e: Correct link check logic for 82571 serdes
SYNCH bit and IV bit of RXCW register are sticky. Before examining these bits, RXCW should be read twice to filter out one-time false events and have correct values for these bits. Incorrect values of these bits in link check logic can cause weird link stability issues if auto-negotiation fails. CC: stable <[email protected]> [2.6.38+] Reported-by: Dean Nelson <[email protected]> Signed-off-by: Tushar Dave <[email protected]> Reviewed-by: Bruce Allan <[email protected]> Tested-by: Jeff Pieper <[email protected]> Signed-off-by: Jeff Kirsher <[email protected]>
-rw-r--r--drivers/net/ethernet/intel/e1000e/82571.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/e1000e/82571.c b/drivers/net/ethernet/intel/e1000e/82571.c
index 36db4df09aed..1f063dcd8f85 100644
--- a/drivers/net/ethernet/intel/e1000e/82571.c
+++ b/drivers/net/ethernet/intel/e1000e/82571.c
@@ -1572,6 +1572,9 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
ctrl = er32(CTRL);
status = er32(STATUS);
rxcw = er32(RXCW);
+ /* SYNCH bit and IV bit are sticky */
+ udelay(10);
+ rxcw = er32(RXCW);
if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {