diff options
| author | Marijn Suijten <[email protected]> | 2021-09-11 14:13:36 +0200 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2021-09-14 14:40:32 -0700 |
| commit | ce336a51deed2397917e9fce7c017004315bd5a5 (patch) | |
| tree | b75a530050e57d0f2f9f3d7a90ec5480c970646d | |
| parent | 9d67de94e1cf8dcd3107def6e1e8b49a9402fad7 (diff) | |
clk: qcom: gpucc-msm8998: Use ARRAY_SIZE for num_parents
Where possible, use ARRAY_SIZE to determine the number of parents in
clk_parent_data, instead of hardcoding it.
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: Marijn Suijten <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
| -rw-r--r-- | drivers/clk/qcom/gpucc-msm8998.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/clk/qcom/gpucc-msm8998.c b/drivers/clk/qcom/gpucc-msm8998.c index fedfffaf0a8d..3ac6fbfbd414 100644 --- a/drivers/clk/qcom/gpucc-msm8998.c +++ b/drivers/clk/qcom/gpucc-msm8998.c @@ -126,7 +126,7 @@ static struct clk_rcg2 rbcpr_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "rbcpr_clk_src", .parent_data = gpu_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gpu_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -144,7 +144,7 @@ static struct clk_rcg2 gfx3d_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gfx3d_clk_src", .parent_data = gpu_xo_gpupll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gpu_xo_gpupll0), .ops = &clk_rcg2_ops, .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, }, @@ -163,7 +163,7 @@ static struct clk_rcg2 rbbmtimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "rbbmtimer_clk_src", .parent_data = gpu_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gpu_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -184,7 +184,7 @@ static struct clk_rcg2 gfx3d_isense_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gfx3d_isense_clk_src", .parent_data = gpu_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gpu_xo_gpll0), .ops = &clk_rcg2_ops, }, }; |