diff options
| author | Deepak S <[email protected]> | 2015-07-10 18:31:40 +0530 |
|---|---|---|
| committer | Daniel Vetter <[email protected]> | 2015-07-13 11:27:21 +0200 |
| commit | cd25dd5b766858b730af00d5b2bbaf6ad2b80c27 (patch) | |
| tree | 45dcfc4848f18bb166a93a9ce920e3a48cfb6325 | |
| parent | feecb691007831263e6285a25a323f175a081f42 (diff) | |
drm/i915: Update PM interrupts before updating the freq
Currently we update the freq before masking the interrupts, which can
allow new interrupts to occur before the frequency has changed. These
extra interrupts might waste some cpu cycles. This patch corrects
this by masking interrupts prior to updating the frequency.
Note from Chris:
"Well it won't waste CPU cycles as the interrupt is also masked by the
threshold limits, but there should be no harm at all in reordering the
patch so, and it does make a certain amount of sense."
Signed-off-by: Deepak S <[email protected]>
Signed-off-by: Praveen Paneri <[email protected]>
Reviewed-by: Chris Wilson <[email protected]>
[danvet: Add note from Chris.]
Signed-off-by: Daniel Vetter <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9d98f4074eae..135fb974dfff 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4482,14 +4482,14 @@ static void valleyview_set_rps(struct drm_device *dev, u8 val) "Odd GPU freq value\n")) val &= ~1; + I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); + if (val != dev_priv->rps.cur_freq) { vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); if (!IS_CHERRYVIEW(dev_priv)) gen6_set_rps_thresholds(dev_priv, val); } - I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); - dev_priv->rps.cur_freq = val; trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); } |