diff options
| author | Varadarajan Narayanan <[email protected]> | 2023-08-31 14:58:53 +0530 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2023-09-19 20:02:18 -0700 |
| commit | ccd8ab030643040600a663edde56b434b6f4fb6c (patch) | |
| tree | ab673f93442e1087637961f5574d7a68e1b5b7b8 | |
| parent | 07c34b37bd955bb62486da1326569ad855f50c69 (diff) | |
clk: qcom: ipq5332: Drop set rate parent from gpll0 dependent clocks
IPQ5332's GPLL0's nominal/turbo frequency is 800MHz.
This must not be scaled based on the requirement of
dependent clocks. Hence remove the CLK_SET_RATE_PARENT
flag.
Fixes: 3d89d52970fd ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC")
Signed-off-by: Varadarajan Narayanan <[email protected]>
Reviewed-by: Kathiravan T <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
| -rw-r--r-- | drivers/clk/qcom/gcc-ipq5332.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c index b02026f8549b..b836159fbdef 100644 --- a/drivers/clk/qcom/gcc-ipq5332.c +++ b/drivers/clk/qcom/gcc-ipq5332.c @@ -71,7 +71,6 @@ static struct clk_fixed_factor gpll0_div2 = { &gpll0_main.clkr.hw }, .num_parents = 1, .ops = &clk_fixed_factor_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -85,7 +84,6 @@ static struct clk_alpha_pll_postdiv gpll0 = { &gpll0_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; |