diff options
| author | Alex Deucher <[email protected]> | 2024-04-14 13:51:37 -0400 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2024-05-08 15:17:06 -0400 |
| commit | cacbbfbd24422c0b7bdb2a689dce4b822001bc84 (patch) | |
| tree | 59059ef66cd4cf0ac2961c268db2f989afdca193 | |
| parent | 42ad8ac6bd3722a04abd1feb630f69ead6b24433 (diff) | |
drm/amdgpu: add set_reg_remap callback for NBIO 7.2
This will be used to consolidate the register remap offset
configuration and fix HDP flushes on systems non-4K pages.
Reviewed-by: Felix Kuehling <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c index e962821ae6a1..52774a096350 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c @@ -408,6 +408,21 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev) regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; } +#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) + +static void nbio_v7_2_set_reg_remap(struct amdgpu_device *adev) +{ + if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) { + adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; + adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; + } else { + adev->rmmio_remap.reg_offset = + SOC15_REG_OFFSET(NBIO, 0, + regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; + adev->rmmio_remap.bus_addr = 0; + } +} + const struct amdgpu_nbio_funcs nbio_v7_2_funcs = { .get_hdp_flush_req_offset = nbio_v7_2_get_hdp_flush_req_offset, .get_hdp_flush_done_offset = nbio_v7_2_get_hdp_flush_done_offset, @@ -429,4 +444,5 @@ const struct amdgpu_nbio_funcs nbio_v7_2_funcs = { .ih_control = nbio_v7_2_ih_control, .init_registers = nbio_v7_2_init_registers, .remap_hdp_registers = nbio_v7_2_remap_hdp_registers, + .set_reg_remap = nbio_v7_2_set_reg_remap, }; |