diff options
| author | Nicholas Kazlauskas <[email protected]> | 2023-11-07 11:15:16 -0500 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2023-11-29 17:58:18 -0500 |
| commit | cab667a87133d409ff18913fd53c2324803ea8d2 (patch) | |
| tree | 131131e118308a0d97c1214e18a5c2b5ad8c9bec | |
| parent | 4b27a33c3b173bef1d19ba89e0b9b812b4fddd25 (diff) | |
drm/amd/display: Feed SR and Z8 watermarks into DML2 for DCN35
[Why]
We've updated the table but the values aren't being reflected in DML2
calculation.
[How]
Pass them into the bbox overrides.
Reviewed-by: Jun Lei <[email protected]>
Acked-by: Hamza Mahfooz <[email protected]>
Signed-off-by: Nicholas Kazlauskas <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c index 30d78ad91b9c..21c17d3296a3 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c @@ -329,6 +329,15 @@ void dcn35_update_bw_bounding_box_fpu(struct dc *dc, /*temp till dml2 fully work without dml1*/ dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31); + + /* Update latency values */ + dc->dml2_options.bbox_overrides.dram_clock_change_latency_us = dcn3_5_soc.dram_clock_change_latency_us; + + dc->dml2_options.bbox_overrides.sr_exit_latency_us = dcn3_5_soc.sr_exit_time_us; + dc->dml2_options.bbox_overrides.sr_enter_plus_exit_latency_us = dcn3_5_soc.sr_enter_plus_exit_time_us; + + dc->dml2_options.bbox_overrides.sr_exit_z8_time_us = dcn3_5_soc.sr_exit_z8_time_us; + dc->dml2_options.bbox_overrides.sr_enter_plus_exit_z8_time_us = dcn3_5_soc.sr_enter_plus_exit_z8_time_us; } static bool is_dual_plane(enum surface_pixel_format format) |